1. Field of the Invention
The present invention generally relates to a gate driver of a liquid crystal display (LCD) panel, and more particularly to a gate driver having a power sequence control circuit.
2. Description of Related Art
In a typical driving system of a conventional LCD, it is desired to apply voltages in a proper sequence. Otherwise, it may cause unusual displaying, or even damages. For example, when applying a gate high voltage VGH and a gate low voltage VGL to a gate driver, an error of sequence in enabling these two voltages may cause a failure in operation of the circuit, e.g., latch-up, and even a damage to the integrate circuit (IC). The gate high voltage VGH and the gate low voltage VGL are an operation positive voltage and an operation negative voltage respectively, which are usually provided by a power block and transmitted to the gate driver. If the VGH signal enters the gate driver earlier than the VGL signal or the two voltages simultaneously enter the gate driver, a transient current may occur. Because generally the VGL voltage is usually coupled to the substrate, when the transient current flows to the substrate, the VGL voltage will be pulled up. When the VGL voltage becomes greater than 0.5 to 0.7V because of pull up effect, a latch-up phenomenon will occur, or a large current may be generated and thus damaging the IC.
In order to avoid the foregoing problems, e.g., damaging the IC, the VGL signal is desired to enter the gate driver earlier than the VGH signal. Generally, the power block provides a gate high voltage VGHp, and a gate low voltage VGLp, in which “p” means that the voltage (VGHp or VGLp) is outputted from the power block and has not yet been entered into the gate driver. Before the VGHp and VGLp enter the gate driver, a sequence of providing the power must be adjusted by external elements or a timing controller, so as to have VGLg entering the gate driver earlier than VGHg, in which “g” means that the voltage (VGHg or VGLg) is actually inputted to the gate driver.
FIG. 1 is a schematic diagram illustrating a general structure of a conventional LCD device. Referring to FIG. 1, a timing controller 100 is a core block provided for controlling an action timing of the display. The timing controller 100 determines horizontal scanning enabling, and converts video signals inputted from an interface into data signals usable for a source driver 102, e.g., RGB data, according to a display timing of each frame. The data signals are transmitted to a memory of the source driver 102, and are cooperated with the horizontal scanning to control the gate driver 102 with a proper timing.
A power block 110 is provided with an external power source VDD. Controlled by the timing controller 100, the power block 110 generates a plurality of voltage levels, and provides these voltage levels to the timing controller 100, the source driver 102, and the gate driver 104. Controlled by the timing controller 100, the source driver 102 stores digital video signals inputted with a high frequency into the memory, and converts the digital video signals into voltages desired to output to a sub-pixel 108, according to an enabling of a particular scan line, so as to drive data lines S1, . . . , Sn of the pixel display panel 106.
Controlled by the timing controller 100, the gate driver 104 sequentially outputs suitable ON/OFF voltages to particular scan lines G1 through Gn, for driving the scan lines of the pixel display panel 106. The pixel display panel 106 is constituted of a plurality of pixels, where each pixel comprises a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Each sub-pixel includes a thin film transistor (TFT) having a gate terminal which is controlled by a scan driving circuit for controlling the ON/OFF status of the TFT. When the TFT is at an ON status, a source terminal of the TFT charges a capacitor of the TFT to a voltage level corresponding to the received data. A twist angle of liquid crystal molecules is determined according to the voltage level, and therefore the grey level of the image performance while the liquid crystal molecules are illuminated by a backlight can be determined. Color filters then combine sub-pixels of different grey levels on the display panel to obtain desired colors, which constitute a high resolution image.
As discussed above, if the voltage signals VGHp, VGLp provided by the power block 110 are directly inputted into the gate driver 104, it cannot be assured that the VGLp signal will be inputted earlier than the VGHp. As such, conventionally, an external circuit 112 is employed to control the sequence of inputting the voltages, so as to properly provide the VGHg, VGLg to the gate driver 104.
Conventionally, there are many approaches to change the sequence of providing power sources. FIG. 2 is a schematic diagram illustrating a conventional mechanism for changing the sequence of providing power sources. Referring to FIG. 2, it illustrates a conventional RC delay method, in which the VGHp signal provided by the power block 110 is delayed and enters the gate driver 104 later than the VGLp signal. As shown in the upper part of FIG. 2, the VGHp signal is delayed by a delay time T, thus entering the gate driver 104 later than the VGLp signal. This approach is simple while having its disadvantages. For example, the delay time is determined by a value of R×C. However, it is often not appropriate to integrate the resistor R and the capacitor C inside the IC, because they occupy area and increase production cost. Even though it can be achieved by external components, the external components also increase the production cost. Further, an external capacitor usually has a large capacitance, and therefore when turning off the power, the large capacitance may cause the VGHg voltage unable to discharge very quickly. Further, in this case, when the power is turned on again, the circuit may be damaged.
Further, another approach is to employ a timing controller to control the sequence of the VGH signal and the VGL signal entering the gate driver. However, this requires an external resistor and capacitor, or an external timing control signal for controlling the sequence of the VGH signal and the VGL signal, which increase the complexity and the production cost.